The present invention relates to a transmitting/receiving signal processing circuit in a digital cordless communication device, and more particularly to a transmitting/receiving signal processing circuit which incorporates a frequency-discrimination demodulator and a frequency synthesized local oscillator comprised of a heterodyne phase locked loop (PLL) for high speed switching.
In the late 1980's and early 1990's, a second generation of digital cordless telephones (CT2) using a frequency division multiple access-time division duplexing (FDMA-TDD) method was introduced. This method has proven to be effective in the field of telecommunications.
In designing transceivers for digital cordless telephones that perform this or other methods of communication, accurate generation of frequencies for signal transmission and reception is always a key concern. Many devices employ one or more phase locked loops (PLL) in order to generate desired frequencies. One such device is disclosed in U.S. application Ser. No. 08/402,506 entitled Transceiver Signal Processor For Digital Cordless Communication Apparatus, assigned to the same assignee as the present invention.
Another device is disclosed in U.S. Pat. No. 5,423,075 entitled Combined Radio Transmission And Reception Apparatus With A PLL Circuit issued to Boese et al. on 6 Jun. 1995. In Boese et al. '075, a transceiver having a transmitting section and a receiving section is provided with a single phase locked loop (PLL) to which the two sections have alternating access. While conventional art such as Boese et al. '075 has merit in its own right, I have learned that an improved device which performs effective high speed frequency switching can be contemplated.